1. Field of the Invention
The present invention relates to the field of digital communications and more particularly to a method for converting digital samples.
2. Description of the Related Art
The field of digital communications is constantly developing and communication rates increase continuously.
Considering a digital communication system""s architecture, it must be reminded that, typically, a digital signalxe2x80x94generally a series of symbols to be transmittedxe2x80x94is converted into a continuous time analog signal which is in turn transmitted by a physical propagation medium, air or any other physical medium of propagation. Upon reception by a receiver, the signal is then processed and converted into a digital form by means of an adequate sample, which generally operates at a frequency fe which is generally made synchronous with the frequency fs to the symbol""s transmission. Unfortunately, oscillator circuits provided within the emitter and the receiver are never synchronous and any frequency offset between the emission and reception clocks must then be compensated in order to allow for correct processing of the received signal and reading of emitted symbols. Frequency compensation at reception is typically carried out with a voltage-controlled oscillator circuit, which is controlled by a clocking circuit which estimates the amount of frequency offset that must be compensated for.
Unfortunately, voltage controlled circuits and controlled sampling circuits are inaccurate, complex analog devices, which are costly to implement and allow little flexibility in signal processing. Currently overall digital processing of information is widely preferred in transmission systems comprising as few analog only circuits as possible.
It is therefore desirable to avoid using voltage-controlled circuits, or even a controlled sampler. It is desirable to be allowed to realize free sampling of an analog signal and then to convert digital samples at another frequency.
An embodiment of the present invention is aimed at providing a device for digitally converting the sampling rate of a sequence of digital samples X(n) inputted at a frequency fe and converted into an output sequence Y(m) outputted with a frequency fs.
Another embodiment of the present invention provides an analog signal sampling device which requires no voltage-controlled oscillator to realize the controlled sampling.
An embodiment of the invention includes a device which automatically converts an input digital sample sequence X(n) at a first frequency fe into an output digital sample sequence Y(m) with a second frequency fs smaller than fe. An interpolator-decimator assembly with a decimation rate equal to xcex3 chosen to correspond to the frequency offset fe/fs is based on a polyphased filter having p tables of q elements each, said filter being adapted to receive samples X(n) delivered at a frequency fe and said filter polyphased components are successively activated according to clocking of a second clock derived from the fi, clock and which lacks clock pulses.
Preferably, this device comprises a clocking unit to successively activate polyphased components at the output frequency fs clocking and a filter output sequence Y(m) selection circuit to keep only the correct sequence of samples corresponding to an interpolation-decimation to a non-integer factor.
In an embodiment, a counter is used to generate a signal each time operand xcex3m⊕1 reaches an integer value, which is used to control said data Y(m) selection circuit.
In a preferred embodiment, the device is provided with an interpolator decimator based on a polyphased filter, which comprises a series of p=2N+1 tables each having a set of q factors used to calculate a convolution between an interpolation/decimation filter and a vector X(n) corresponding to the input digital sample sequence.